1. Field of the Invention
The present invention relates to a semiconductor integrated circuit design apparatus and a semiconductor integrated circuit design method.
2. Description of the Related Art
In recent years, the number of circuits included in a semiconductor integrated circuit has been remarkably increased as the semiconductor integrated circuit has been minitualized. This results in difficulty in testing operations of the circuits included in the semiconductor integrated circuit. For this reason, various DFT (Design for Testability) techniques have been developed.
One of the DFT techniques is a scan path method in which scan cells for detecting failure are provided in the semiconductor integrated circuit. In the scan path method, the scan cell is connected to wiring between gates included in the semiconductor integrated circuit. A point on the wiring to which the scan cell is connected is called an observation point. In the scan path method, a test signal is inputted to the semiconductor integrated circuit, and an output signal outputted through the scan cell is detected, whereby an operation of the semiconductor integrated circuit is tested.
However, when the scan cells are provided in the semiconductor integrated circuit, an area of the semiconductor integrated circuit is increased.
Japanese Patent Laid-Open No. 2002-131391 describes a semiconductor integrated circuit in which a spare cell used at the time of correcting the semiconductor integrated circuit is employed as a scan cell. In this semiconductor integrated circuit, since the spare cell is used as the scan cell, this reduces an increase in area of the semiconductor integrated circuit due to provision of a dedicated scan cell in the semiconductor integrated circuit
However, in this semiconductor integrated circuit, when the spare cell and the observation point are connected to each other, no consideration is given to the array positions of the spare cell and the observation point, and the length of wiring connecting the spare cell to the observation point. Accordingly, in this semiconductor integrated circuit, when the spare cell and the observation point are connected to each other by the wiring, there is a possibility that the length of the wiring connecting the spare cell to the observation point is increased, so that delay may occur in the operation of the semiconductor integrated circuit.